The present invention relates generally to digital electronic circuits, and, more particularly, to a level shifter circuit.
Modern day systems-on-a-chips (SoCs) are designed to consume less power by using lower operating voltages. Multiple voltage domains operating at different voltage supply levels are used to decrease the overall operating voltage of the SoC. These multiple voltage domains require stepping up/down of voltage levels of signals that cross different voltage domains. Level shifter circuits are used to step up/down the logic signal level as it enters a different voltage level domain.
Conventional level shifter circuits operate by using at least two voltage supplies to step up/down the voltage level of the input signal. The two voltage supplies include high and low voltage supplies that correspond to the voltage supply levels of the domains between which the signal traverses. The two voltage supplies require two separate routing tracks for each row of standard cells in the SoC design. Since the circuit densities of SoCs are continually rising, placement and routing of standard cells is becoming increasingly onerous. The requirement of additional routing tracks to route the two voltage supplies for the level shifter circuits adds to placement and routing complexities and leads to congestion in functional nets. To overcome the above-mentioned difficulties, level shifters that use a single voltage supply have been designed.
FIG. 1 shows a schematic circuit diagram of a conventional level shifter circuit 100 that operates using a single voltage supply. The level shifter circuit 100 includes six transistors (first through sixth) 102-112.
Source and gate terminals of the first transistor 102 are connected to a voltage supply (Vddh). A source terminal of the second transistor 104 is connected to the voltage supply Vddh. A drain terminal of the second transistor 104 is connected to drain and source terminals of the first and third transistors 102 and 106, respectively. A gate terminal of the third transistor 106 receives an input voltage (Vin). A drain terminal of the fourth transistor 108 is connected to a drain terminal of the third transistor 106, a gate terminal of the fourth transistor 108 is connected to the gate terminal of the third transistor 106 for receiving the input voltage Vin, and a source terminal of the fourth transistor 108 is connected to ground. Further, a source terminal of the fifth transistor 110 is connected to the voltage supply Vddh, and a gate terminal thereof is connected to the drain terminals of the third and fourth transistors 106 and 108. A drain terminal of the sixth transistor 112 is connected to a drain terminal of the fifth transistor 110, a gate terminal of the sixth transistor 112 is connected to the gate terminal of the fifth transistor 110, and a source terminal of the sixth transistor 112 is connected to ground. The drain terminals of the fifth and sixth transistors 110 and 112 are connected to a gate terminal of the second transistor 104. An output voltage Vout is generated at the drain terminals of the fifth and sixth transistors 110 and 112.
A voltage at the source terminal of the third transistor 106 is dynamically changed based on the input voltage Vin using the second transistor 104, thereby generating the output voltage Vout that is a level-shifted form of the input voltage Vin. For example, when the input voltage Vin is HIGH (i.e., 1.8V), the third transistor is switched off. The successive inverters formed by the third and fourth transistors 106 and 108 and fifth and sixth inverters 110 and 112 invert the input voltage Vin twice leading to the output voltage Vout becoming HIGH. The output voltage Vout is provided at the gate terminal of the second transistor 104 that is switched off by the output voltage Vout being HIGH. Since the first transistor 102 is a diode-connected transistor, a voltage at its drain terminal is Vddh−Vt (Vt is the threshold voltage drop of the first transistor 102).
When the input voltage Vin is LOW (i.e., ˜1.0V), the output voltage Vout remains LOW. The LOW output voltage Vout switches on the second transistor 104, which pulls up the voltage at the gate terminal thereof and at the source terminal of the third transistor 106 to Vddh. Thus, the voltage at the source terminal of the third transistor 106 is dynamically switched between Vddh−Vt and Vddh leading to the generation of the output voltage Vout that is a level-shifted form of the input voltage Vin.
Since the level shifter circuit 100 operates with just one voltage supply, it overcomes limitations associated with dual voltage supply level shifters. However, the level shifter circuit 100 still suffers from several disadvantages. For example, if the difference between (Vddh−Vt) and the input voltage Vin is more than Vt, then a leakage current is generated. If the input voltage Vin=0.75V, the voltage supply Vddh=1.42V, and the threshold voltage Vt=0.28V, then since Vddh−Vt=1.14V and Vddh−Vt−Vin=0.39V (which is greater than Vt=0.28V), a high leakage currents flow through the first, third, and fourth transistors 102, 106 and 108, which deteriorates the functionality of the convention level shifter circuit 100 and limit its use in applications having broad input and output voltage ranges. Additionally, the first transistor 102 is a diode-connected transistor, which limits the operating speed of the conventional level shifter circuit 100.
Therefore, it would be advantageous to have a level shifter circuit that uses a single voltage supply, that has a fast operating speed and reduced leakage currents, and that overcomes the above-mentioned limitations of the conventional level shifter circuits.